Recently, flat-panel displays have a larger screen and higher definition, while establishing reduction in thickness, weight, and cost. With such backgrounds, it is required for display drivers to improve the uniformity in the displayed image qualities through decreasing variations between output electric currents that are outputted from output terminals. Variations in the electric currents in static actions of current mirrors include variations caused due to fabrication processes of each transistor, variations of gate voltages caused due to resistances of power supply wirings, and the like. Further, variations due to dynamic actions of the current mirrors include variations caused due to injection of electric charges from a display panel or instantaneous fluctuations of power supply, for example. Furthermore, generally, a driver IC is formed in a multi-output structure with a stick-like slim shape, since it is mounted to a frame part of a flat panel. Because of restrictions in the LSI shape, characteristics of transistors disposed therein vary depending on positions of slim-layout elements. Therefore, even if a same gate voltage is applied in a current mirror structure, the output currents from each of current-summing DA converter circuits do not necessarily become the same.
As a method for decreasing such variations, there is a current driving device having a current output part, such as the one shown in FIG. 6A and FIG. 6B, for example (see US 2005/0231241A1, for example). This current output part has a calibration function and a current output function. “Calibration” means to have a reference current value by a reference current source stored in the current output part.
Under a calibration mode, current output switches So1 and So2 are set to a nonconductive state, while a current input switch Sw1, a calibration switch Sw2, and all signal response switches G1-Gm are set to a conductive state. Current output terminals T1 and T2 are isolated from the outside. Nodes N1 and N2 are short-circuited, and drains and gates of Nch transistors QN1-QNm are short-circuited to receive electric currents from a reference current source I1. Through this, the Nch transistors QN1-QNm generate, at the node N2, a gate voltage that is necessary for allowing the electric current from the reference current source I1 to flow through the transistors themselves. A voltage holding capacitance element C1 is charged to the above-described gate voltage. A voltage V (N2) of the node N2 corresponds to a voltage that is capable of passing an electric current that is equal to the reference current generated by the reference current source I1 through the Nch transistors QN1-QNm which are all in a conductive state. In conclusion, the current output part A comes to store the reference current generated by the reference current source I1.
Under a current output mode, the current input switch Sw1 and the calibration switch Sw2 are turned to a nonconductive state, and either one of the current output switch So1 or So2 is set to a conductive state while the other is remained in a nonconductive state. The conduction state of the signal response switches G1-Gm is determined depending on an input signal supplied from the outside. The voltage holding capacitance element C1 holds the voltage charged by the calibration action, and continues to supply the electric current to the gate terminals of the Nch transistors QN1-QNm. The Nch transistors QN1-QNm output an electric current in accordance with the voltage V (N2) of the node N2 from one (in an conductive state) of the current output terminals T1 and T2, in accordance with the conduction state of the signal response switches G1-Gm.
FIG. 7 shows a timing chart of a series of actions regarding calibration and output of the electric current performed in the current-summing DA converter circuit shown in FIG. 6A and FIG. 6B. The conductive state of the switches is shown with “H”, and the nonconductive state thereof is shown with “L”. “V (N2)” indicates the voltage V (N2) of the node N2.
Before calibration, the current output part A sets the current output witch So1 to be in a conductive state, and outputs, from the current output terminal T1, the output current in accordance with the state of the signal response switches G1-Gm which are controlled by the voltage V (N2) of the node N2 and an input signal. The current output switch So2, the current input switch Sw1, and the calibration switch Sw2 are set to be in a nonconductive state.
During the calibration period, the current output switches So1, So2 are set to a nonconductive state, the current input switch Sw1 and the calibration switch Sw2 are set to a conductive state, and the signal response switches G1-Gm for selecting the electric currents from the Nch transistors QN1-QNm are all set to a conductive state. Through this, the Nch transistors QN1-QNm are set in a state where only the electric current of the reference current source I1 is supplied, and the voltage V (N2) of the node N2 is determined in accordance with the above-described actions.
After completing the above-described calibration, the current input switch Sw1 and the calibration switch Sw2 are set to a nonconductive state, so that the voltage holding capacitance element C1 holds the electric charge. That is, the voltage V (N2) of the node N2 is being maintained. Thereafter, the current output switch So2 is set to a conductive state, and the sum of the electric currents selected by the signal response switches G1-Gm in accordance with the input signal is outputted from the current output terminal T2.
FIG. 8 shows a structure of a current driving device that utilizes the current output part A shown in FIG. 6A and FIG. 6B. (n+1)-numbers of current output parts A0-An control the operation states under a calibration mode and a current output mode in accordance with control signals supplied from an action control circuit B. A signal input circuit Din supplies signals for controlling the signal response switches G1-Gm within the internal structural elements (see FIG. 6A) of each of the current output parts A0-An. Calibration by the reference current source I1 is performed on a single current output part among the (n+1)-numbers of current output parts A0-A1 by an internal operation of each of the current output parts A0-An. Calibration is performed in order from A0, to A1, A2, - - - , and to An. The current output parts that are not under calibration are set to be in the current output mode, and output an electric current to n-numbers of output terminals OUT1-OUTn. The electric currents are outputted in order from A0 to A1, A2, - - - , and to An.
The reference current, when there are a plurality of current-summing DA converter circuits with the above-described current output parts, can be combined into the electric currents of the same current source. This makes it possible to achieve the uniformity in the display on a panel.
Other related documents are: Japanese Unexamined Patent Publication 2004-219955, Japanese Unexamined Patent Publication 2005-121843, US2004/0251844A1, US7050024B2, US6594606B2, US2006/0158402A1.
With this method, however, the capacity for charging/discharging the voltage holding capacitance element C1 becomes insufficient when the current value of the reference current source I1 is very small, so that it is difficult to charge the current of the Nch transistors QN1-QNm to accurately meet the value of the current from the reference current source I1 within the calibration period. FIG. 9 shows the state where the voltage holding capacitance element C1 is insufficiently charged because the reference current is very small.
Further, when there is a change in the current value of the reference current source I1, the reference currents become varied depending on the output terminals with the successive calibration, until the reference currents of all the current output parts A0-An are updated.